1 ps2038b 01/10/01 logic block diagram 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 product features: common features: ? pi74fct16543t, pi74fct162543t and pi74fct162h543t are high-speed, low power devices with high current drive. ?v cc = 5v 10% ? hysteresis on all inputs ? packages available: C 56-pin 240 mil wide plastic tssop (a) C 56-pin 300 mil wide plastic ssop (v) pi74fct16543t features: ? high output drive: i oh = C32 ma; i ol = 64 ma ? power off disable outputs permit live insertion ? typical v olp (output ground bounce) < 1.0v at v cc = 5v, t a = 25c pi74fct162543t features: ? balanced output drivers: 24 ma ? reduced system switching noise ? typical v olp (output ground bounce) < 0.6v at v cc = 5v, t a = 25c pi74fct162h543t features: ? bus hold retains last active state during 3-state ? eliminates the need for external pull-up resistors product description: pericom semiconductors pi74fct series of logic circuits are pro- duced in the companys advanced 0.6 micron cmos technology, achieving industry leading speed grades. the pi74fct16543t, pi74fct162543t and pi74fct162h543t are 16- bit latched transceivers organized with two sets of eight d-type latches with separate input and output controls for each set. for data flow from a to b, for example, the a-to-b enable (xceab) input must be low in order to enter data from xax or to take data from xbx, as indicated in the truth table. with xceab low, a low signal makes the a-to-b latches transparent; a subsequent low-to-high transition of the xleab signal puts the a latches in the storage mode and their outputs no longer change the a inputs. with xceab and xoeab both low, the 3-state b output buffers are active and reflect the data present at the output of the a latches. control of data from b to a is similar, but uses the xceba, xleba, and xoeba inputs. the pi74fct16543t output buffers are designed with a power-off disable allowing live insertionof boards when used as backplane drivers. the pi74fct162543t has 24 ma balanced output drivers. it is designed with current limiting resistors at its outputs to control the output edge rate resulting in lower ground bounce and undershoot. this eliminates the need for external terminating resistors for most interface applications. the pi74fct162h543t has bus hold which retains the inputs last state whenever the input goes to high-impedance preventing floating inputs and eliminating the need for pull-up/down resistors. pi74fct16543t pi74fct162543t pi74fct162h543t fast cmos 16-bit latched transceivers 1 b 0 d c 1 a 0 to 7 other channels d c 1 leab 1 ceab 1 oeab 1 leba 1 ceba 1 oeba 2 b 0 d c 2 a 0 to 7 other channels d c 2 leab 2 ceab 2 oeab 2 leba 2 ceba 2 oeba
pi74fct16543/162543/162h543t 16-bit latched transceivers 2 ps2038b 01/10/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 25 26 27 28 32 31 30 29 1 oeab 1 leab 1 ceab gnd 1 a 0 1 a 1 vcc 1 a 2 1 a 3 1 a 4 gnd 1 a 5 1 a 6 1 a 7 2 a 0 2 a 1 2 a 2 gnd 2 a 3 2 a 4 2 a 5 v cc 2 a 6 2 a 7 gnd 2 ceab 2 leab 2 oeab 1 oeba 1 leba 1 ceba gnd 1 b 0 1 b 1 vcc 1 b 2 1 b 3 1 b 4 gnd 1 b 5 1 b 6 1 b 7 2 b 0 2 b 1 2 b 2 gnd 2 b 3 2 b 4 2 b 5 v cc 2 b 6 2 b 7 gnd 2 ceba 2 leba 2 oeba product pin description pin name description xoeab a-to-b output enable input (active low) xoeba b-to-a output enable input (active low) xceab a-to-b enable input (active low) xceba b-to-a enable input (active low) xleab a-to-b latch enable input (active low) xleba b-to-a latch enable input (active low) xax a-to-b data inputs or b-to-a 3-state outputs (1) xbx b-to-a data inputs or b-to-a 3-state outputs (1) gnd ground v cc power latch output inputs status buffers x ceab x leab x oeab x a x to x b xx b x h x x storing high z x h x storing x x x h x high z l l l transparent current a inputs l h l storing previous* a inputs truth table (1) notes: 1. *before xleab low-to-high transistion h = high voltage level l = low voltage level x = dont care or irrelevant z = high impedance 2. a-to-b data flow shown. b-to-a flow control is the same, except using xceba, xleba, and xoeba. note: 1. for the pi74fct162h543t, these pins have bus hold. all other pins are standard, outputs, or i/os. product pin configuration 56-pin v56 a56
pi74fct16543/162543/162h543t 16-bit latched transceivers 3 ps2038b 01/10/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 dc electrical characteristics (over the operating range, t a = C40c to +85c, v cc = 5.0v 10%) parameters description test conditions (1) min. typ (2) max. units v ih input high voltage guaranteed logic high level 2.0 v v il input low voltage guaranteed logic low level 0.8 v i ih input high current standard input, v cc = max. v in = v cc 1a i ih input high current standard i/o, v cc = max. v in = v cc 1a i ih input high current bus hold input (4) , v cc = max. v in = v cc 100 a i ih input high current bus hold i/o (4) , v cc = max. v in = v cc 100 a i il input low current standard input, v cc = min. v in = gnd C1 a i il input low current standard i/o, v cc = min. v in = gnd C1 a i il input low current bus hold input (4) , v cc = min. v in = gnd 100 a i il input low current bus hold i/o (4) , v cc = min. v in = gnd 100 a i bhh bus hold bus hold input (4) , v cc = min. v in = 2.0v C50 a i bhl sustain current v in = 0.8v +50 i ozh (5) high-impedance v cc = max. v out = 2.7v 1 a i ozl (5) output current v cc = max. v out = 0.5v C1 a (3-s tate o utputs ) v ik clamp diode voltage v cc = min., i in = C18 ma C0.7 C1.2 v i os short circuit current v cc = max. (3) , v out = gnd C80 C140 C200 ma i o output drive current v cc = max. (3) , v out = 2.5v C50 C180 ma v h input hysteresis 100 mv maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) storage temperature .................................................................... C65c to +150c ambient temperature with power applied .................................... C40c to +85c supply voltage to ground potential (inputs & vcc only) .............. C0.5v to +7.0v supply voltage to ground potential (outputs & d/o only) ........... C0.5v to +7.0v dc input voltage ............................................................................ C0.5v to +7.0v dc output current ..................................................................................... 120 ma power dissipation .......................................................................................... 1.0w note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at vcc = 5.0v, +25c ambient and maximum loading. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. pins with bus hold are identified in the pin description. 5. this specification does not apply to bi-directional functionalities with bus hold.
pi74fct16543/162543/162h543t 16-bit latched transceivers 4 ps2038b 01/10/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct16543t output drive characteristics (over the operating range) parameters description test conditions (1) min. typ (2) max. units v oh output high voltage v cc = min., v in = v ih or v il i oh = C3.0 ma 2.5 3.5 v i oh = C15.0 ma 2.4 3.5 i oh = C32.0 ma 2.0 3.0 v ol output low voltage v cc = min., v in = v ih or v il i ol = 64 ma 0.2 0.55 v i off power down disable v cc = 0v, v in or v out 4.5v 100 a pi74fct162543t/162h543t output drive characteristics (over the operating range) parameters description test conditions (1) min. typ (2) max. units v oh output high voltage v cc = min., v in = v ih or v il i oh = C24.0 ma 2.4 3.3 v v ol output low voltage v cc = min., v in = v ih or v il i ol = 24 ma 0.3 0.55 v i odl output low current v cc = 5v, v in = v ih or v il , v out = 1.5v (3) 60 115 150 ma i odh output high current v cc = 5v, v in = v ih or v il , v out = 1.5v (3) C60 C115 C150 ma notes: 1. for max. or min.conditions, use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at vcc = 5.0v, +25c ambient and maximum loading. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. this parameter is determined by device characterization but is not production tested. capacitance (t a = 25c, f = 1 mhz) parameters (4) description test conditions typ max. units c in input capacitance v in = 0v 4.5 6 pf c out output capacitance v out = 0v 5.5 8 pf
pi74fct16543/162543/162h543t 16-bit latched transceivers 5 ps2038b 01/10/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 power supply characteristics parameters description test conditions (1) min. typ (2) max. units i cc quiescent power v cc = max. v in = gnd or v cc 0.1 500 a supply current d i cc supply current per v cc = max. v in = 3.4v (3) 0.5 1.5 ma input @ ttl high i ccd supply current per v cc = max., outputs open v in = v cc 60 100 a/ input per mhz (4) xceab & xoeab = gnd v in = gnd mhz xceba = v cc one bit toggling 50% duty cycle i c total power supply v cc = max., v in = v cc 0.6 1.5 (5) ma current (6) outputs open v in = gnd f i = 10 mh z 50% duty cycle xleab, xceab, and v in = 3.4v 0.9 2.3 (5) xoeab = gnd v in = gnd xceba = v cc one bit toggling v cc = max., v in = v cc 2.4 4.5 (5) outputs open v in = gnd f i = 2.5 mh z 50% duty cycle xleab, xceab, and v in = 3.4v 6.4 16.5 (5) xoeab = gnd v in = gnd xceba = v cc 16 bits toggling notes: 1. for max. or min. conditions , use appropriate value specified under electrical characteristics for the applicable device. 2. typical values are at vcc = 5.0v, +25c ambient. 3. per ttl driven input (v in = 3.4v); all other inputs at vcc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the icc formula. these limits are guaranteed but not tested. 6. i c =i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp /2 + f i n i ) i cc = quiescent current d i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = input frequency n i = number of inputs at f i all currents are in milliamps and all frequencies are in megahertz.
pi74fct16543/162543/162h543t 16-bit latched transceivers 6 ps2038b 01/10/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct16543t switching characteristics over operating range 16543t 16543at 16543ct 16543dt 16543et com. com. com. com. com. parameters description conditions (1) min max min max min max min max min max unit t plh propagation delay c l = 50 pf 2.5 8.5 2.5 6.5 2.5 5.3 2.5 4.4 1.5 3.4 ns t phl transparent mode r l = 500 w xax to xbx or xbx to xax t plh propagation delay 2.5 12.5 2.5 8.0 2.5 7.0 2.5 5.0 1.5 3.7 ns t phl xleba to xax, xleab to xbx t pzh output enable time 2.0 12.0 2.0 9.0 2.0 8.0 2.0 5.4 1.5 4.8 ns t pzl xoeba or xoeab to xax or xbx t phz output disable time (3) 2.0 9.0 2.0 7.5 2.0 6.5 2.0 4.3 1.5 4.0 ns t plz xoeba or xoeab to xax or xbx t su setup time high or low 3.0 2.0 2.0 2.0 1.0 ns xax or xbx to xleab or xleba t h hold time high or low 2.0 2.0 2.0 1.5 1.0 ns xax or xbx to xleab or xleba t w xleab or xleba pulse width 5.0 5.0 5.0 3.0 3.0 3.0 ns low (3) t sk (o) output skew (4) 0.5 0.5 0.5 0.5 0.5 ns notes: 1. see test circuit and wave forms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. this parameter is guaranteed but not production tested. 4. skew between any two outputs, of the same package, switching in the same direction. this parameter is guaranteed by design. pi74fct162543t switching characteristics over operating range 162543t 162543at 162543ct 162543dt 162543et com. com. com. com. com. parameters description conditions (1) min max min max min max min max min max unit t plh propagation delay c l = 50 pf 2.5 8.5 2.5 6.5 2.5 5.3 2.5 4.4 1.5 3.4 ns t phl transparent mode r l = 500 w xax to xbx or xbx to xax t plh propagation delay 2.5 12.5 2.5 8.0 2.5 7.0 2.5 5.0 1.5 3.7 ns t phl xleba to xax, xleab to xbx t pzh output enable time 2.0 12.0 2.0 9.0 2.0 8.0 2.0 5.4 1.5 4.8 ns t pzl xoeba or xoeab to xax or xbx t phz output disable time (3) 2.0 9.0 2.0 7.5 2.0 6.5 2.0 4.3 1.5 4.0 ns t plz xoeba or xoeab to xax or xbx t su setup time high or low 3.0 2.0 2.0 2.0 1.0 ns xax or xbx to xleab or xleba t h hold time high or low 2.0 2.0 2.0 1.5 1.0 ns xax or xbx to xleab or xleba t w xleab or xleba pulse width 5.0 5.0 5.0 3.0 3.0 3.0 ns low (3) t sk (o) output skew (4) 0.5 0.5 0.5 0.5 0.5 ns
pi74fct16543/162543/162h543t 16-bit latched transceivers 7 ps2038b 01/10/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct162h543t switching characteristics over operating range 162h543t 162h543at 162h543ct 162h543dt 162h543et com. com. com. com. com. parameters description conditions (1) min max min max min max min max min max unit t plh propagation delay c l = 50 pf 2.5 8.5 2.5 6.5 2.5 5.3 2.5 4.4 1.5 3.4 ns t phl transparent mode r l = 500 w xax to xbx or xbx to xax t plh propagation delay 2.5 12.5 2.5 8.0 2.5 7.0 2.5 5.0 1.5 3.7 ns t phl xleba to xax, xleab to xbx t pzh output enable time 2.0 12.0 2.0 9.0 2.0 8.0 2.0 5.4 1.5 4.8 ns t pzl xoeba or xoeab to xax or xbx t phz output disable time (3) 2.0 9.0 2.0 7.5 2.0 6.5 2.0 4.3 1.5 4.0 ns t plz xoeba or xoeab to xax or xbx t su setup time high or low 3.0 2.0 2.0 2.0 1.0 ns xax or xbx to xleab or xleba t h hold time high or low 2.0 2.0 2.0 1.5 1.0 ns xax or xbx to xleab or xleba t w xleab or xleba pulse width 5.0 5.0 5.0 3.0 3.0 3.0 ns low (3) t sk (o) output skew (4) 0.5 0.5 0.5 0.5 0.5 ns notes: 1. see test circuit and wave forms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. this parameter is guaranteed but not production tested. 4. skew between any two outputs, of the same package, switching in the same direction. this parameter is guaranteed by design. pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com
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